Fault-Tolerant Implementation of Systolic Arrays

In this paper, several fault-tolerant hardware implementations of Systolic Arrays on reconfigurable devices, such as FPGAs, are investigated and primal selection criteria such as resource utilization, computation time, advantages and disadvantages of every fault-tolerant method are presented. Since the main goal of the designs presented herein is the high performance of the implementations, the obtained Systolic Arrays for each of the investigated fault-tolerant method are space-optimal and time-optimal, i.e., they have minimal number of Processing Elements for the given problem size and they have minimal execution time for that number of Processing Elements, respectively. Systolic networks are a class of pipelined array architectures which rhythmically compute and pass data through the complex. A Systolic Array features the important properties of modularity, regularity, spatial locality, temporal locality, high degree pipelinability, parallel computing and high synchronized multiprocessing. The VLSI technology advance enables the integration of circuits with millions of components into a single silicon chip and has opened the way for massive parallel computations. In order to take advantage of the computational specialization and the inherent parallelism of Systolic Arrays, a proper platform for their implementation is reconfigurable devices, such as FPGAs, since, in applications that permit parallelization, FPGAs can be used as dedicated computers in order to perform certain computations at very high frequencies. Their flexibility and the simplicity of the existing software design tools make FPGAs a suitable platform for rapid system prototyping. Over the above, FPGAs, as a middle ground between software and ASICs (Application Specific Integrated Circuits), offer the designer the benefits of custom hardware, eliminating high development costs and manufacturing time.